EMSNow - Indium Corporation Technology Expert to Present at IMAPS Advanced Technology Workshop

EMSNow - Indium Corporation Technology Expert to Present at IMAPS Advanced Technology Workshop: Indium Corporation's Brook Sandy-Smith, Product Support Specialist - PCB Assembly Materials, will present at the International Microelectronics and Packaging Society (IMAPS) Advanced Technology Workshop on Microelectronic Packaging for Medical and Hi-Reliability Devices May 13-14 in Minneapolis,

Sandy-Smith will present the following papers:

• A Low-Silver SAC Solder Alloy for High-Reliability Applications. This presentation examines the reliability of a low-Ag SAC solder alloy doped with Mn (SACM). SACM is compared to eutectic SnPb, SAC105, SAC305 alloys under various test conditions, such as JEDEC drop shock, dynamic bending, thermal cycling, and cyclic bending.

• Soldering Technologies Enabling Medical Device Packaging in the 3D Era. This paper will review the various forms of soldering for medical electronics and other types of medical devices. It examines how soldering technology is evolving to meet the challenges of smaller devices, which are more sensitive to manufacturing processes. Flux and similar materials that enable new assembly processes in the era of 2.5D and 3D technology will also be discussed.

Sandy-Smith serves as a technical liaison between Indium Corporation's customers and internal departments, such as research and development and production, to ensure the best quality and selection of products. She earned two degrees from the international engineering program at the University of Rhode Island: one in chemical engineering with a focus on materials, the other in German language.

SMTONLINE IPC Conference Centers on Medical Device Manufacturing

SMTONLINE  Electronic medical device manufacturers are under constant pressure to deliver innovative products on time and within budget, while contending with rapidly changing technologies, increasing product complexity, and strict compliance and safety standards across a global marketplace. To help address these challenges, IPC — Association Connecting Electronics Industries� will host a one-and-a-half day conference, “Innovations in Electronics in Manufacturing for Medical Devices,” June 12-13, 2013 in Minneapolis, Minnesota.

 “Global regulations, lead-free technology, evolving manufacturing processes, reliability demands, and R&D issues are transforming the way medical device companies manage their supply chains,” said Sanjay Huprikar, IPC vice president of member success. “This conference is focused on the innovations taking place in electronics manufacturing at every stage of the medical devices supply chain.”

Subject matter experts from Mayo Clinic, Medtronic, Philips Healthcare, Boston Scientific, St. Jude Medical, Micro Systems Engineering, Sanmina Corporation, Celestica, Jabil, Benchmark Electronics, Endicott Interconnect Technologies, Indium, HDPUG, Frost and Sullivan, and more will help attendees identify new market forces driving cost reductions, discover new lead-free technology breakthroughs, address sustainability challenges, and obtain practical and advanced manufacturing techniques for the age of miniaturization.

Critical concerns in soldering reactions arising from space confinement in 3-D IC packages

Scopus: Six critical issues relating to interfacial reactions arising from space confinement in 3-D integrated-circuit (3-D IC) packaging are presented in this paper. The first issue arises from the concern that intermetallics (IMCs) may occupy a large portion of the solder joint volume.

It will be demonstrated that this concern is real even for Ni under bump metallurgy (UBM) or surface finish, which reacts very slowly with solders. The second issue relates to impingement and ripening of IMC grains. When IMCs occupy a large portion of a joint, the IMC grains growing from the opposite sides of a joint will eventually touch each other. The morphology evolution from this point on determines the final microstructure of a joint. Structural defects might form as a result of the impingement and ripening of IMC grains. The third issue is the rise of impurity concentration due to solder consumption. Many of the impurities in solders, such as those from electroplating, are not soluble in IMCs. As Sn reacts to form IMCs, these impurities are rejected from IMCs into the remaining solder. Consequently, the concentrations of these impurities increase with the progress of reaction. Eventually, these impurities are trapped between IMCs growing from the opposite directions. The impact of these trapped impurities on the properties of solder joints is an important issue. The fourth issue is similar to the third except that the role of impurities is replaced by inert alloy elements of solders. The most obvious element is Ag. The fifth issue arises from the fact that, as the size of a joint becomes smaller, the surface-area-to- volume ratio increases. This makes the impact of thin-film layers on UBM and surface finish become ever higher. One well-known element is Au. The so-called Au embrittlement issue may become relevant again. The last issue is the volume shrinkage from chemical reactions. Internal stress or structure defects may form because of this shrinkage. Experimental evidence will be used in this paper to illustrate these six issues, and the implications of these issues will be discussed.

(This is inside components rather than on PCB's but still interesting perhaps? - Jeremy)

   
IEEE Transactions on Device and Materials Reliability
Volume 12, Issue 2, 2012, Article number 6135780, Pages 233-240
Critical concerns in soldering reactions arising from space confinement in 3-D IC packages

Chuang, H.Y., Yang, T.L., Kuo, M.S., Chen, Y.J., Yu, J.J., Li, C.C., Kao, C.R.  

Department of Materials Science and Engineering, National Taiwan University, Taipei 10617, Taiwan

PCB Technology Trends 2011

PCB Technology Trends 2011: This global study of technology trends in the PCB industry is based on an extensive survey in which 41 leading PCB companies from all regions of the world participated. It covers issues in PCB technology today and expectations for developments through 2014. Topics include trends in high-density interconnect (HDI) and microvias, miniaturization in PCB production, solder mask, final finishes, metals, substrate materials, laminates, embedded technology, printed electronics, optics and manufacturing equipment. Sales growth drivers, the impact on sourcing, technical challenges and unmet technology needs are also explored.

Lead-free solder foil for use in component packaging - stacked semiconductor wafers

US20120111924A1: According to an aspect of the invention, there is provided a lead-free solder including an alloy rolled into a shape of sheet. The alloy includes: tin; from 10 wt % to less than 25 wt % of silver; and from 3 wt % to 5 wt % of copper. And the alloy is free from lead.
The alloy may include 10 wt % to 20 wt % of silver. The alloy may have a shape of sheet with a thickness from 40 μm to 120 μm. The alloy may have a shape of a disk with the same diameter as a joined member, for example, a semiconductor wafer.
According to another aspect of the invention, the solder or materials thereof are not powdered, and thin sheet-shaped lead-free solder which is an alloy containing tin, silver, and copper as main components can be obtained.
The lead-free solder according to the present invention has an advantage in that, the solder and materials thereof are alloyed and rolled in a shape of a thin sheet without powdering the solder and materials thereof, so that costs are reduced.

MAKITA, Kazuyuki; Tokyo, Japan
ICHINOSE, Masaki; Tokyo, Japan
WATASHIMA, Taketo; Tokyo, Japan
SOUTOME, Masayuki; Tokyo, Japan
YAMASHITA, Mitsuo; Tokyo, Japan
ASAGI, Takeshi; Tokyo, Japan
HIRAI, Masatoshi; Tokyo, Japan
MURATA, Toru; Tokyo, Japan

Assignee:     FUJI ELECTRIC SYSTEMS CO., LTD., Tokyo, Japan
other patents from FUJI ELECTRIC SYSTEMS CO., LTD. (844106) (approx. 1)
 News, Profiles, Stocks and More about this company

Published / Filed:     2012-05-10 / 2012-01-18

Manufacturability & Reliability Challenges with LNCSP Packages in Lead-Free Processes

SMTONLINE: Leadless, near chip scale packages (LNCSP), like the quad flat pack no lead (QFN), are the fastest growing package types in the electronics industry today. Early LNCSPs were fairly straightforward components with small overall dimensions, a single outer row of leads, and small lead counts. However, there is currently a proliferation of advanced LNCSP package styles that have started to approach BGA packages in terms of both size and number of connections. Some of the newer packages have three or more rows, pitches as fine as 0.35 mm, lead counts exceeding 200, and dimensions exceeding 12 mm x 12 mm

While the advantages of these packages are well documented, concerns arise with both reliability and manufacturability in lead-free environments. So, acceptance of these packages in long-life, severe environment, high-reliability applications is somewhat limited. One of the most common drivers for reliability failures is the inappropriate adoption of new technologies like LNCSP. Since robust manufacturing and qualifications standards always lag behind implementation, users must carefully select and validate these components for suitability in their use environments and customer applications.

Soldering, flexure, and cleanliness issues have driven many failures seen in production and in the field. All of these areas must be addressed early in the selection and validation processes. In this paper, we will review and discuss LNCSP-related reliability concerns and challenges, and propose physics-of-failure (PoF)-based approaches to allow the successful introduction and failure analysis of LNCSP components in electronics products.

Method to form solder deposits on substrates

(EP2416634A1: Described is a method of forming a solder deposit on a substrate comprising the following steps i) provide a substrate (102) including a permanent resin layer (103) on top of at least one contact area (101) and a temporary resin layer (104) on top of the permanent resin layer (103), ii) contact the entire substrate area including the at least one contact area (101) with a solution suitable to provide a conductive layer (106) on the substrate surface, iii) electroplate a solder deposit layer (107) containing tin or a tin alloy onto the conductive layer (106) and iv) etch away an amount of the solder deposit layer (107) containing tin or a tin alloy sufficient to remove the solder deposit layer (107) from the temporary resin layer (104) area leaving a solder material layer (107) on the at least one contact area (101).

Currently, the most common method for formation of presolder bumps on the circuit board is the stencil printing method. Some prior proposals in relation to the stencil printing method can be referred to U.S. Pat. No. 5,203,075 (C. G. Angulas et al.), U.S. Pat. No. 5,492,266 (K. G. Hoebener et al.) and U.S. Pat. No. 5,828,128 (Y. Higashiguchi et al.). Solder bumping technique for flip chip assemblies requires design considerations regarding both bump pitch and size miniaturization. According to practical experiences, the stencil printing will become infeasible once the bump pitch is decreased below 0.15 millimeter. In contrast, the solder bumps deposited by electroplating offer the ability to further reduce bump pitch down to below 0.15 millimeter.

EP European Patent Office (EPO)
A1 APPLICATION PUBLISHED WITH SEARCH REPORT i


Inventor: Matejat, Kai-Jens; 14109, Berlin, Germany
Lamprecht, Sven; 16727, Oberkrämer/Eichstädt, Germany
Ewert, Ingo; 14167, Berlin, Germany

Assignee: ATOTECH Deutschland GmbH, 10553 Berlin, Germany

Pulse electroplating of Sn-Bi alloys on micropatterned electrodes for lead-free solder bumping

Scopus: Pulse plating of Sn-Bi alloys was performed in a simple binary Sn 2 -Bi 3 bath containing citric acid (CA), ethylenediaminetetraacetic acid (EDTA), and poly- ethylene glycol (PEG400) at pH = 1 under 70 of duty percentage and 10 Hz of pulse frequency on polyimide-micropatterned CuNi substrates (denoted as mPI-CN).

From the chronopotentiometric and scanning electron microscopic (SEM) studies, the edge effect of mass transport for Bi 3 resulted in the composition variation between edge and central regions. The increase in the Sn content of Sn-Bi deposits reduces the dendrite formation in the edge region. Through adjusting the concentration of Bi 3 ions and the current density of pulse deposition, uniform morphologies and compositions of Sn-Bi deposits could be obtained. From the demonstration shown in this work, the pulse plating method provided a reliable route to obtain uniform Sn-Bi alloys of high Sn contents (e.g., 80Sn-20Bi and 90Sn-10Bi) for the micro-sized lead-free solder bumping

Tsai, Y.-D., Yu, C.-Y., Hu, C.-C. , Duh, J.-G.

Department of Chemical Engineering, National Tsing Hua University, Hsin-Chu 30013, Taiwan

Journal of the Electrochemical Society
Volume 159, Issue 2, 2012, Pages D108-D113

Packaging Community Takes on New Challenges through Industry Collaboration

SEMI.ORG: The collaborative work of the packaging programs committees has also produced outstanding sessions focused on the intersection of semiconductor packaging technology and business.

In the second half of 2011 alone, the Americas Advanced Packaging Committee developed sessions which brought together industry leaders in 3D and 2.5D as well as heterogeneous integration of devices, while at the same time keep a focus on developments on packaging technologies that are needed in the near term.

The SEMI Taiwan Packaging & Testing Committee developed the inaugural SiP Global Summit, which was a three-day intense look at 3D-IC packaging and test technologies as well as embedded substrates.

The Advanced Packaging Committee of Europe delivered two half-day sessions at SEMICON Europe which took a hard look specifically at manufacturability with respect to technologies, materials, processes and equipment.

And the Japan Packaging Committee developed two sessions of strong technical content covering 3D-ICs, TSVs, system scaling and integration, and interconnect in conjunction with the SEMI Technology Symposium (STS).

Speedprint Reports Strongest Year

EMSNow: Speedprint's results have been fuelled by the increasing focus of customers on excellence in print quality combined with value for money.

In 2011 Speedprint entered the North American market with a direct operation headed by Mark Brawley, Speedprint Americas VP of Sales. The introduction of Speedprint in the United States is already ahead of the company's plans and continues to grow in momentum.

At the same time, the success of the Speedprint products generally is generating increasing interest from China where the company has yet to establish a dedicated sales channel.

Solder Volume Effects on the Microstructure Evolution and Shear Fracture Behavior of Ball Grid Array Structure Sn-3.0Ag-0.5Cu Solder Interconnects

Scopus: The standoff height of ball grid array (BGA) structure solder joints has a significant influence on the formation and growth of interfacial intermetallic compounds (IMC).

The results show that the thickness of the IMC layer at the solder/Cu interface of BGA structure Cu/Sn-3.0Ag-0.5Cu/Cu joints increases with decreasing standoff height after reflowing. The growth behavior of the total IMC layer is controlled by a diffusion process with the growth rate increasing with standoff height.

Both the standoff height and isothermal aging time greatly influence the shear behavior of joints, the shear strength of which shows a parabolic trend with increasing standoff height, while the nominal shear strain decreases monotonically with increasing standoff height.

The fracture location of BGA structure joints changed from the middle of the solder matrix to near the interface when the standoff height was increased.

After undergoing isothermal aging at 125C, the fracture mechanism of solder joints changed from ductile fracture to the mixed mode of brittle and ductile fracture with increasing standoff height

Solder bump with inner core pillar in semiconductor package

US8039960: An electrical interconnect within a semiconductor device consists of a substrate with a plurality of active devices.

A contact pad is formed on the substrate in electrical contact with the plurality of active devices. A passivation layer, first barrier layer, adhesion layer, and seed layer are formed over the substrate. An inner core pillar including a hollow interior is centered over and formed within a footprint of the contact pad.

A second barrier layer and a wetting layer are formed over the single cylindrical inner core pillar and hollow interior.

A spherical bump is formed around the second barrier layer, wetting layer, and single cylindrical inner core pillar. A footprint of the spherical bump encompasses the footprint of the contact pad. The spherical bump is electrically connected to the contact pad

Effects of different solder alloys on reliability of 3D PLUS solder joint

Scopus: Thermal cycling was applied to assess the effect of tin-lead solder 63Sn37Pb and lead-free solder 95.5Sn3.8Ag0.7Cu on the reliability of 3D PLUS solder joints. Nonlinear finite element method and viscoplastic Anand model were used to evaluate the stress and strain distribution and dangerous position of solders under the thermal cycling condition. The law of solder joints stress and plastic strain were finally obtained and showed significant cyclical changes. The stress and strain emerged the trend of accumulated enhancement with the process of time, then ultimately stabilized. Comparing two curves of equivalent stress and plastic strain obtained from lead-free and tin-lead solder, it was found that the reliability of 95.5Sn3.8Ag0.7Cu was better than that of 63Sn37Pb

Advanced Materials Research

Volume 314-316, 2011, Pages 1038-1042

Bao, N., Wang, C., Zhu, L., Song, S.

School of Mechanical Engineer and Automation, Beihang University, Beijing 100191, China

Effect on lead-free solder joint reliability caused by solder volume - Welding International - Volume 25, Issue 11

Welding International - Volume 25, Issue 11: Welding International

Volume 25, Issue 11, 2011

Effect on lead-free solder joint reliability caused by solder volume

Mitsuharu Yamabea, Masako Fukumitsua & Yoshitoshi Fukuchia
pages 851-856

Available online: 22 Sep 2011

Effects of bump size on deformation and fracture behavior of Sn3.0Ag0.5Cu/Cu solder joints during shear testing

Scopus: To elaborate deformation and fracture behavior of Sn3.0Ag0.5Cu/Cu solder joint, dynamic shear testing was designed and performed on as-reflowed and aged solder joints which contained limited numbers of grains. Polarized light microscopy (PLM) and electron backscatter diffraction (EBSD) were used to reveal the grain morphology and the grain distribution.

Scanning electron Microscopy (SEM) was applied to observe the influences of microstructures and intermetallic compounds (IMCs) on the solder joints fracture behavior. The experimental results suggested that the morphology and distribution of IMCs (Cu6Sn5 and Ag3Sn) were the main reasons for the size effect in Sn3.0Ag0.5Cu solder joints.

The shear strength of as-reflowed and aged solder joints decreased with the increased joint sizes. The nano-scale particle-like Ag3Sn dispersed in the small solder joints had a strengthen effect on their mechanical property. While the dendritic and feather-like Ag3Sn brought the big solder joints the brittleness.

Furthermore, obvious plastic deformation in company with dynamic recovery and recrystallization was observed in small solder joints during dynamic shear testing. The fracture occurred in the bulk solder. While the brittle fracture occurred in big solder joints and the fracture positions were at the areas close to the soldering interface.

The cracks propagated by the way of transgranular fracture. After aging, dynamic recovery and recrystallization occurred in all solder joints. While the plasticity of big solder joint was enhanced and the transgranular fracture as well as the intergranular fracture occurred during dynamic shear testing

Tian, Y.a b , Hang, C.a b , Wang, C.a b , Yang, S.b , Lin, P.b

a State Key Lab of Advanced Welding and Joining, Harbin Institute of Technology, Harbin 150001, PR China

b Department of Electronics Packaging Technology, Harbin Institute of Technology, Harbin 150001, PR China

Effects of Co additions on electromigration behaviors in Sn-3.0 Ag-0.5 Cu-based solder joint

Scopus: "As the miniaturization trend of electronic packing industry, electromigration (EM) has become a critical issue for fine pitch packaging. The EM effects on microstructure evolution of intermetallic compound layer (IMC) in Sn-3.0 Ag-0.5 Cu XCo (X = 0, 0.05, 0.2 wt%) solder joint was investigated.

Findings of this study indicated that current stressing of Sn-3.0 Ag-0.5 Cu-0.2 Co solder joint with 104 A/cm2 at 50 'C for 16 days, no remarkable EM damages exhibited in solder matrix. Whereas, after current stressing at 150 'C for 1 and 3 days, Sn-3.0 Ag-0.5 Cu specimens showed obvious polarity effect between cathode and anode. Different morphology changes were also observed at both sides.

After current stressing for 1 day, two IMC layers, Cu6Sn5 and Cu3Sn, with wave type morphology formed at cathode. Sn phases were also observed inside in the IMC layer. However, only Cu6Sn5 formed in anode. Three days later, Sn phases were found in anode. Besides, Co additions, aging treatment, Ag3Sn, and other IMCs improved the resistance of EM by the evidence of retarding polarity effect"

Copper pillar to be mainstream FC packaging technology in 2012

Digitimes: "IC packagers Advanced Semiconductor Engineering (ASE), Amkor Technology, Siliconware Precision Industries (SPIL) and STATS ChipPAC have all started developing a new flip-chip (FC) packaging technology dubbed copper pillar bumping, according to industry sources. The new packaging method will replace conventional solder bumping as the mainstream technology in 2012.

The transition to a new FC packaging technology is being sped up by growing demand for smaller form factors and low cost products such as smartphones, the sources indicated. Meanwhile, further advances in shrinking process geometries are also required to produce chips with high level of integration and low power consumption. While migrating to smaller-geometry processes, reducing manufacturing costs has become more fundamental for chip companies, the sources pointed out."

Volume effect on shear strength of SnAgCu lead-free solder joints

Scopus: "Sn3.0Ag0.5Cu lead-free solder joints of different sizes in the range of 200 μm to 600 μm were multi-reflowed and aged, and then the shear strength of those solder joints were tested by the micro-force tester DAGE4000. The effect of solder volume differences on the shear strength of solder joints was investigated. The results indicated that the shear strength of SnAgCu lead-free solder joints decreased with the increasing of the solder joint volume, showing an apparent volume effect. The effect of aging time and reflow times on the shear strength of solder joints with different sizes were also discussed, and scanning electron microscopy (SEM) was used to analyze the morphology of shear fracture, and the failure mechanism of solder joints were discussed."

Wang, C., Wang, X., Tian, Y.

State Key Laboratory of Advanced Welding Production Technology, Harbin Institute of Technology, Harbin 150001, China

The creep behaviour and microstructure of ultra small solder joints

Scopus: "The creep behavior of Sn-based solders undergoes a significant scaling effect. Therefore this paper compares creep data that was gained on bulky samples and on small solder joints. Optical microscopy techniques and SEM-microprobe analysis were used to examine the microstructural properties of the bulk specimens and real solder joints were after metallographic sectioning. The results of these microstructural analysis were related to the investigated mechanical properties of the solders"

SMART Group Announces Two (FREE) Webinars Covering New EU Projects

EMSNo: "uBGA European Project Update
Tuesday 19th April 2011 at 14.30 GMT

There is relentless consumer demand for electronics equipment offering miniaturisation with higher functionality (e.g. cell phones playing music and movies whilst also offering email/SMS/camera functions). The industry is therefore continuously aiming for increases in integrated circuit miniaturisation, processor speeds and circuit densities. A major interconnection and a vital part of package manufacture for reliable connection is provided by the solder sphere."

This uBGA project will re-evaluate existing manufacturing process, inspection and size control of different solder alloy spheres. It will then produce example packages and demonstrate the reliability through assembly and soldering trials within different industries. If you want an insight into the future of uBGA manufacture and the problems being researched join us for this webinar.

Topics will include:

Project overview, Industry survey, uBGA requirements, solder alloy requirements, solder sphere manufacture, existing process & issues and conclude with future industry benefits.

μBGA is a collaboration project, co-ordinated and managed by KCC Ltd and is partly funded by the EC under the Research for the Benefit of Specific Groups Project ref: FP7-SME-2002-2-GA-263653

BIZESP links with ChinaTin